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| PMN40LN TrenchMOSTM logic level FET M3D302 Rev. 01 -- 13 November 2002 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOSTM technology. Product availability: PMN40LN in SOT457 (TSOP6). 2. Features s TrenchMOSTM technology s Logic level compatible s Surface mount package. 3. Applications s Battery management s High speed switch s Low power DC to DC converter. 4. Pinning information Table 1: Pin 1,2,5,6 3 4 Pinning - SOT457 (TSOP6), simplified outline and symbol Description drain (d) gate (g) source (s) g s 6 5 4 d Simplified outline Symbol 1 Top view 2 3 MBK092 MBB076 SOT457 (TSOP6) Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 5. Quick reference data Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions 25 C Tj 150 C Tsp = 25 C; VGS = 10 V Tsp = 25 C VGS = 10 V; ID = 2.5 A; Tj = 25 C VGS = 4.5 V; ID = 2 A; Tj = 25 C Typ 32 40 Max 30 5.4 1.75 150 38 45 Unit V A W C m m drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tsp = 25 C peak source (diode forward) current Tsp = 25 C; pulsed; tp 10 s Tsp = 25 C; VGS = 10 V; Figure 2 and 3 Tsp = 70 C; VGS = 10 V; Figure 2 Tsp = 25 C; pulsed; tp 10 s; Figure 3 Tsp = 25 C; Figure 1 Conditions 25 C Tj 150 C 25 C Tj 150 C; RGS = 20 k Min -55 -55 Max 30 30 15 5.4 4 21.6 1.75 +150 +150 1.45 5.8 Unit V V V A A A W C C A A Source-drain diode 9397 750 10192 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 2 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 120 Pder (%) 80 03aa17 120 Ider (%) 80 03aa25 40 40 0 0 50 100 150 Tsp (C) 200 0 0 50 100 150 200 Tsp (C) P tot P der = ---------------------- x 100% P tot ( 25 C ) ID I der = ------------------ x 100% I D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature. Fig 2. Normalized continuous drain current as a function of solder point temperature. 102 ID (A) 10 03aj86 Limit RDSon = VDS / ID tp = 10 s 100 s 1 ms 1 10 ms DC 100 ms 10-1 10-2 10-1 1 10 VDS (V) 102 Tsp = 25 C; VGS = 10 V; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 10192 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 3 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 7. Thermal characteristics Table 4: Rth(j-sp) Thermal characteristics Conditions Min Typ Max Unit 70 K/W thermal resistance from junction to solder point mounted on a metal clad board; Figure 4 Symbol Parameter 7.1 Transient thermal impedance 102 Zth(j-sp) (K/W) 03aj85 = 0.5 0.2 10 0.1 0.05 0.02 1 P single pulse tp T = tp T t 10-1 10-4 10-3 10-2 10-1 1 10 tp (s) 102 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration. 9397 750 10192 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 4 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 8. Characteristics Table 5: Characteristics Tj = 25 C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 C Tj = 150 C Tj = -55 C IDSS drain-source leakage current VDS = 24 V; VGS = 0 V Tj = 25 C Tj = 150 C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = 15 V; VDS = 0 V VGS = 4.5 V; ID = 2 A; Figure 7 and 8 Tj = 25 C Tj = 150 C VGS = 10 V; ID = 2.5 A; Figure 7 Tj = 25 C Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 1.7 A; VGS = 0 V; Figure 12 VDD = 15 V; RL = 12 ; VGS = 10 V; RG = 6 VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 ID = 5 A; VDD = 15 V; VGS = 10 V; Figure 13 13.8 1.8 2.4 555 105 70 5 7 19 8 0.8 1.2 nC nC nC pF pF pF ns ns ns ns V 32 38 m 40 64 45 72 m m 0.05 10 1 500 100 A A nA 1 0.6 1.5 2 2.2 V V V 30 27 V V Conditions Min Typ Max Unit Source-drain diode 9397 750 10192 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 5 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 20 ID (A) 15 03aj87 10 V 5 V 4.5 V 4 V 3.6 V 20 ID (A) 15 VDS > ID x RDSon 03aj89 3.2 V 10 3V 10 2.8 V 5 2.6 V VGS = 2.4 V 0 0 0.2 0.4 0.6 0.8 1 VDS (V) 0 0 1 2 3 VGS (V) 4 5 Tj = 150 C 25 C Tj = 25 C Tj = 25 C and 150 C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 80 RDSon (m) 60 Tj = 25 C VGS = 3.2 V 03aj88 2 a 03af18 3.6 V 4V 4.5 V 5V 10 V 1.5 40 1 20 0.5 0 0 5 10 15 ID (A) 20 0 -60 0 60 120 Tj (C) 180 Tj = 25 C R DSon a = --------------------------R DSon ( 25 C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. 9397 750 10192 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 6 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 2.5 VGS(th) (V) 2 max 03aa33 10-1 ID (A) 10-2 03aa36 1.5 typ 10-3 min typ max 1 min 10-4 0.5 10-5 0 -60 0 60 120 Tj (C) 180 10-6 0 1 2 VGS (V) 3 ID = 1 mA; VDS = VGS Tj = 25 C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 103 03aj91 C (pF) Ciss 102 Coss Crss 10 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 9397 750 10192 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 7 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 20 IS (A) 15 VGS = 0 V 03aj90 10 VGS (V) 8 ID = 5 A Tj = 25 C VDD = 15 V 6 03aj92 10 4 150 C 5 2 Tj = 25 C 0 0 0.5 1 VSD (V) 1.5 0 0 4 8 12 QG (nC) 16 Tj = 25 C and 150 C; VGS = 0 V ID = 5 A; VDD = 15 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. 9397 750 10192 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 8 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 9. Package outline Plastic surface mounted package; 6 leads SOT457 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 c 1 2 3 Lp e bp wM B detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.1 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT457 REFERENCES IEC JEDEC EIAJ SC-74 EUROPEAN PROJECTION ISSUE DATE 97-02-28 01-05-04 Fig 14. SOT457 (TSOP6). 9397 750 10192 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 9 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 10. Revision history Table 6: 01 Revision history CPCN Description Product data. Rev Date 20021113 11. Trademarks TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V. 9397 750 10192 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 10 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET 12. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 13. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 14. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 10192 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 13 November 2002 11 of 12 Philips Semiconductors PMN40LN TrenchMOSTM logic level FET Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 (c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 13 November 2002 Document order number: 9397 750 10192 |
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